Sr No Area Page No 1 Microelectronics , VLSI & Display Technology 11 - 26 2 RF Microwaves & Photonics 27 - 36 3 Signal Processing , Communications & Networks 37 - 74 4 Power and Control 75 - 92

A 10 bit current steering CMOS digital-to-analog converter (DAC) is designed, with optimized performance for frequency domain applications. To get the best of both binary-weighted and thermometer-coded architectures, most current-steering D/A converters are implemented using a segmented architecture. Segmentation is chosen to reduce the total area occupied by the DAC. The optimum segmentation found in this design used 6 thermometer-coded bits in the MSB section and 4 binary-weighted bits in the LSB section. With the help of Monte Carlo simulations area of the unit current source is fixed, which satisfy the yield specification of the DAC. This DAC is designed for a yield of 99.73 %. The DNL and INL specifications are chosen to be 0.1 LSB and 0.4 LSB respectively. For a sampling frequency of 100 MSPS, the SFDR is better than 57 dB for signal from dc to 40 MHz. For a sampling frequency of 200 MSPS, the SFDR is better than 49 dB for signals from dc to 80 MHz. When operating at 200 MSPS, it dissipates 12 mW from a 1.8 V power supply. Key building blocks designed for this DAC are current cells, C2MOS register, binary to thermometer decoder, latches and biasing network for current cells. Layouts for these blocks are drawn and all the measurements are taken after back-annotation. This DAC occupied a total area of 0.13 mm2. All the designs are done in 1.8 V, 0.18 μm CMOS technology from GPDK (Generic Process Design Kit) Cadence EDA tool suite For more details click here back